From 1318ff15173310790f51db1f2a298e4c3958798c Mon Sep 17 00:00:00 2001 From: Uwe Lippmann Date: Sun, 22 Sep 2013 21:41:33 +0200 Subject: [PATCH] Finished schematics and preliminary board layout. --- custom_symbols/4007-2.sym | 243 ++++++ custom_symbols/ldr-1.sym | 35 + custom_symbols/led-2.sym | 39 + custom_symbols/speaker-2.sym | 33 + custom_symbols/switch-1.fpt | 12 + custom_symbols/switch-spst-1.sym | 28 + gafrc | 9 + light-theremin.pcb | 1333 ++++++++++++++++++++++++++++++ light-theremin.pro | 2 +- light-theremin.sch | 360 ++++++-- 10 files changed, 2008 insertions(+), 86 deletions(-) create mode 100644 custom_symbols/4007-2.sym create mode 100644 custom_symbols/ldr-1.sym create mode 100644 custom_symbols/led-2.sym create mode 100644 custom_symbols/speaker-2.sym create mode 100644 custom_symbols/switch-1.fpt create mode 100644 custom_symbols/switch-spst-1.sym create mode 100644 gafrc create mode 100644 light-theremin.pcb diff --git a/custom_symbols/4007-2.sym b/custom_symbols/4007-2.sym new file mode 100644 index 0000000..849114a --- /dev/null +++ b/custom_symbols/4007-2.sym @@ -0,0 +1,243 @@ +v 20110115 2 +P 600 900 1000 900 1 0 1 +{ +T 650 900 5 8 0 1 0 8 1 +pintype=out +T 800 950 5 8 1 1 0 0 1 +pinnumber=13 +T 800 850 5 8 0 1 0 2 1 +pinseq=8 +T 650 900 9 8 0 1 0 6 1 +pinlabel=D_P1 +} +P 600 1300 1000 1300 1 0 1 +{ +T 650 1300 5 8 0 1 0 8 1 +pintype=pwr +T 800 1350 5 8 1 1 0 0 1 +pinnumber=14 +T 800 1250 5 8 0 1 0 2 1 +pinseq=7 +T 650 1300 9 8 0 1 0 6 1 +pinlabel=VDD,S_P1 +} +L 600 1400 600 1200 3 0 0 0 -1 -1 +L 600 1000 600 800 3 0 0 0 -1 -1 +L 600 1150 600 1050 3 0 0 0 -1 -1 +L 550 1350 550 850 3 0 0 0 -1 -1 +P 600 100 1000 100 1 0 1 +{ +T 650 100 5 8 0 1 0 8 1 +pintype=pwr +T 800 150 5 8 1 1 0 0 1 +pinnumber=7 +T 800 50 5 8 0 1 0 2 1 +pinseq=10 +T 650 100 9 8 0 1 0 6 1 +pinlabel=VSS,S_N1 +} +P 600 500 1000 500 1 0 1 +{ +T 650 500 5 8 0 1 0 8 1 +pintype=out +T 800 550 5 8 1 1 0 0 1 +pinnumber=8 +T 800 450 5 8 0 1 0 2 1 +pinseq=9 +T 650 500 9 8 0 1 0 6 1 +pinlabel=D_N1 +} +L 600 600 600 400 3 0 0 0 -1 -1 +L 600 350 600 250 3 0 0 0 -1 -1 +L 550 550 550 50 3 0 0 0 -1 -1 +L 550 1350 300 1350 3 0 0 0 -1 -1 +L 300 1350 300 50 3 0 0 0 -1 -1 +L 300 50 550 50 3 0 0 0 -1 -1 +P 300 700 0 700 1 0 1 +{ +T 350 700 5 8 0 1 0 2 1 +pintype=in +T 200 750 5 8 1 1 0 6 1 +pinnumber=6 +T 200 650 5 8 0 1 0 8 1 +pinseq=2 +T 350 700 9 8 0 1 0 0 1 +pinlabel=G1 +} +L 600 200 600 0 3 0 0 0 -1 -1 +L 625 1050 625 1150 3 0 0 0 -1 -1 +L 625 1050 675 1100 3 0 0 0 -1 -1 +L 675 1100 625 1150 3 0 0 0 -1 -1 +L 675 1050 675 1150 3 0 0 0 -1 -1 +L 675 1100 700 1100 3 0 0 0 -1 -1 +L 700 1100 700 1300 3 0 0 0 -1 -1 +L 675 250 675 350 3 0 0 0 -1 -1 +L 675 250 625 300 3 0 0 0 -1 -1 +L 625 300 675 350 3 0 0 0 -1 -1 +L 625 250 625 350 3 0 0 0 -1 -1 +L 675 300 700 300 3 0 0 0 -1 -1 +L 700 100 700 300 3 0 0 0 -1 -1 +L 600 300 625 300 3 0 0 0 -1 -1 +L 600 1100 625 1100 3 0 0 0 -1 -1 +P 3600 900 4000 900 1 0 1 +{ +T 3650 900 5 8 0 1 0 8 1 +pintype=out +T 3800 950 5 8 1 1 0 0 1 +pinnumber=1 +T 3800 850 5 8 0 1 0 2 1 +pinseq=12 +T 3650 900 9 8 0 1 0 6 1 +pinlabel=D_P2 +} +P 3600 1300 4000 1300 1 0 1 +{ +T 3650 1300 5 8 0 1 0 8 1 +pintype=out +T 3800 1350 5 8 1 1 0 0 1 +pinnumber=2 +T 3800 1250 5 8 0 1 0 2 1 +pinseq=11 +T 3650 1300 9 8 0 1 0 6 1 +pinlabel=S_P2 +} +L 3600 1400 3600 1200 3 0 0 0 -1 -1 +L 3600 1000 3600 800 3 0 0 0 -1 -1 +L 3600 1150 3600 1050 3 0 0 0 -1 -1 +L 3550 1350 3550 850 3 0 0 0 -1 -1 +P 3600 100 4000 100 1 0 1 +{ +T 3650 100 5 8 0 1 0 8 1 +pintype=out +T 3800 150 5 8 1 1 0 0 1 +pinnumber=4 +T 3800 50 5 8 0 1 0 2 1 +pinseq=4 +T 3650 100 9 8 0 1 0 6 1 +pinlabel=S_N2 +} +P 3600 500 4000 500 1 0 1 +{ +T 3650 500 5 8 0 1 0 8 1 +pintype=out +T 3800 550 5 8 1 1 0 0 1 +pinnumber=5 +T 3800 450 5 8 0 1 0 2 1 +pinseq=13 +T 3650 500 9 8 0 1 0 6 1 +pinlabel=D_N2 +} +L 3600 600 3600 400 3 0 0 0 -1 -1 +L 3600 350 3600 250 3 0 0 0 -1 -1 +L 3550 550 3550 50 3 0 0 0 -1 -1 +L 3550 1350 3300 1350 3 0 0 0 -1 -1 +L 3300 1350 3300 50 3 0 0 0 -1 -1 +L 3300 50 3550 50 3 0 0 0 -1 -1 +P 3300 700 3000 700 1 0 1 +{ +T 3350 700 5 8 0 1 0 2 1 +pintype=in +T 3200 750 5 8 1 1 0 6 1 +pinnumber=3 +T 3200 650 5 8 0 1 0 8 1 +pinseq=1 +T 3350 700 9 8 0 1 0 0 1 +pinlabel=G2 +} +L 3600 200 3600 0 3 0 0 0 -1 -1 +L 3625 1050 3625 1150 3 0 0 0 -1 -1 +L 3625 1050 3675 1100 3 0 0 0 -1 -1 +L 3675 1100 3625 1150 3 0 0 0 -1 -1 +L 3675 1050 3675 1150 3 0 0 0 -1 -1 +L 3675 1100 3700 1100 3 0 0 0 -1 -1 +L 3800 1100 3700 1100 3 0 0 0 -1 -1 +L 3675 250 3675 350 3 0 0 0 -1 -1 +L 3675 250 3625 300 3 0 0 0 -1 -1 +L 3625 300 3675 350 3 0 0 0 -1 -1 +L 3625 250 3625 350 3 0 0 0 -1 -1 +L 3675 300 3700 300 3 0 0 0 -1 -1 +L 3800 300 3700 300 3 0 0 0 -1 -1 +L 3600 300 3625 300 3 0 0 0 -1 -1 +L 3600 1100 3625 1100 3 0 0 0 -1 -1 +P 6700 700 7000 700 1 0 1 +{ +T 6650 700 5 8 0 1 0 8 1 +pintype=out +T 6800 750 5 8 1 1 0 0 1 +pinnumber=12 +T 6800 650 5 8 0 1 0 2 1 +pinseq=5 +T 6650 700 9 8 0 1 0 6 1 +pinlabel=D_N/P3 +} +P 6600 1300 7000 1300 1 0 1 +{ +T 6650 1300 5 8 0 1 0 8 1 +pintype=out +T 6800 1350 5 8 1 1 0 0 1 +pinnumber=11 +T 6800 1250 5 8 0 1 0 2 1 +pinseq=14 +T 6650 1300 9 8 0 1 0 6 1 +pinlabel=S_P3 +} +L 6600 1400 6600 1200 3 0 0 0 -1 -1 +L 6600 1000 6600 800 3 0 0 0 -1 -1 +L 6600 1150 6600 1050 3 0 0 0 -1 -1 +L 6550 1350 6550 850 3 0 0 0 -1 -1 +P 6600 100 7000 100 1 0 1 +{ +T 6650 100 5 8 0 1 0 8 1 +pintype=out +T 6800 150 5 8 1 1 0 0 1 +pinnumber=9 +T 6800 50 5 8 0 1 0 2 1 +pinseq=6 +T 6650 100 9 8 0 1 0 6 1 +pinlabel=S_N3 +} +L 6600 600 6600 400 3 0 0 0 -1 -1 +L 6600 350 6600 250 3 0 0 0 -1 -1 +L 6550 550 6550 50 3 0 0 0 -1 -1 +L 6550 1350 6300 1350 3 0 0 0 -1 -1 +L 6300 1350 6300 50 3 0 0 0 -1 -1 +L 6300 50 6550 50 3 0 0 0 -1 -1 +P 6300 700 6000 700 1 0 1 +{ +T 6350 700 5 8 0 1 0 2 1 +pintype=in +T 6200 750 5 8 1 1 0 6 1 +pinnumber=10 +T 6200 650 5 8 0 1 0 8 1 +pinseq=3 +T 6350 700 9 8 0 1 0 0 1 +pinlabel=G3 +} +L 6600 200 6600 0 3 0 0 0 -1 -1 +L 6625 1050 6625 1150 3 0 0 0 -1 -1 +L 6625 1050 6675 1100 3 0 0 0 -1 -1 +L 6675 1100 6625 1150 3 0 0 0 -1 -1 +L 6675 1050 6675 1150 3 0 0 0 -1 -1 +L 6675 1100 6700 1100 3 0 0 0 -1 -1 +L 6800 1100 6700 1100 3 0 0 0 -1 -1 +L 6675 250 6675 350 3 0 0 0 -1 -1 +L 6675 250 6625 300 3 0 0 0 -1 -1 +L 6625 300 6675 350 3 0 0 0 -1 -1 +L 6625 250 6625 350 3 0 0 0 -1 -1 +L 6675 300 6700 300 3 0 0 0 -1 -1 +L 6800 300 6700 300 3 0 0 0 -1 -1 +L 6600 300 6625 300 3 0 0 0 -1 -1 +L 6600 1100 6625 1100 3 0 0 0 -1 -1 +L 6600 900 6700 900 3 0 0 0 -1 -1 +L 6600 500 6700 500 3 0 0 0 -1 -1 +L 6700 500 6700 900 3 0 0 0 -1 -1 +T 100 1500 8 10 1 1 0 0 1 +refdes=U? +T 800 4800 5 10 0 0 0 0 1 +device=4007 +T 800 5200 5 10 0 0 0 0 1 +footprint=DIP14 +T 800 5400 5 10 0 0 0 0 1 +description=dual complementary pair and inverter +T 800 5000 5 10 0 0 0 0 1 +numslots=0 diff --git a/custom_symbols/ldr-1.sym b/custom_symbols/ldr-1.sym new file mode 100644 index 0000000..2b5a9d9 --- /dev/null +++ b/custom_symbols/ldr-1.sym @@ -0,0 +1,35 @@ +v 20110115 2 +P 800 400 600 400 1 0 0 +{ +T 700 450 5 8 0 1 0 0 1 +pinnumber=2 +T 700 450 5 8 0 0 0 0 1 +pinseq=2 +T 700 450 5 8 0 1 0 0 1 +pinlabel=2 +T 700 450 5 8 0 1 0 0 1 +pintype=pas +} +P 0 400 200 400 1 0 0 +{ +T 100 450 5 8 0 1 0 0 1 +pinnumber=1 +T 100 450 5 8 0 0 0 0 1 +pinseq=1 +T 100 450 5 8 0 1 0 0 1 +pinlabel=1 +T 100 450 5 8 0 1 0 0 1 +pintype=pas +} +B 200 300 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 350 5 10 0 0 0 0 1 +device=RESISTOR +T 0 800 8 10 1 1 0 0 1 +refdes=R? +V 400 400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 950 850 700 600 3 0 0 0 -1 -1 +L 850 950 600 700 3 0 0 0 -1 -1 +L 700 600 800 650 3 0 0 0 -1 -1 +L 700 600 750 700 3 0 0 0 -1 -1 +L 600 700 650 800 3 0 0 0 -1 -1 +L 600 700 700 750 3 0 0 0 -1 -1 diff --git a/custom_symbols/led-2.sym b/custom_symbols/led-2.sym new file mode 100644 index 0000000..f4f43a6 --- /dev/null +++ b/custom_symbols/led-2.sym @@ -0,0 +1,39 @@ +v 20110115 2 +T 800 300 8 10 1 1 0 0 1 +refdes=D? +T 100 600 8 10 0 0 0 0 1 +device=LED +P 0 100 200 100 1 0 0 +{ +T 100 150 5 8 0 1 0 0 1 +pinnumber=1 +T 100 150 5 8 0 0 0 0 1 +pinseq=1 +T 100 150 5 8 0 1 0 0 1 +pinlabel=1 +T 100 150 5 8 0 1 0 0 1 +pintype=pas +} +P 900 100 700 100 1 0 0 +{ +T 700 150 5 8 0 1 0 0 1 +pinnumber=2 +T 700 150 5 8 0 0 0 0 1 +pinseq=2 +T 700 150 5 8 0 1 0 0 1 +pinlabel=2 +T 700 150 5 8 0 1 0 0 1 +pintype=pas +} +L 300 200 500 100 3 0 0 0 -1 -1 +L 500 100 300 0 3 0 0 0 -1 -1 +L 300 200 300 0 3 0 0 0 -1 -1 +L 500 200 500 0 3 0 0 0 -1 -1 +L 500 100 700 100 3 0 0 0 -1 -1 +L 300 100 200 100 3 0 0 0 -1 -1 +L 430 240 530 340 3 0 0 0 -1 -1 +L 530 340 480 310 3 0 0 0 -1 -1 +L 530 340 500 290 3 0 0 0 -1 -1 +L 500 240 600 340 3 0 0 0 -1 -1 +L 600 340 550 310 3 0 0 0 -1 -1 +L 600 340 570 290 3 0 0 0 -1 -1 diff --git a/custom_symbols/speaker-2.sym b/custom_symbols/speaker-2.sym new file mode 100644 index 0000000..6b6c733 --- /dev/null +++ b/custom_symbols/speaker-2.sym @@ -0,0 +1,33 @@ +v 20110115 2 +L 1000 1500 1000 500 3 0 0 0 -1 -1 +T 100 300 9 10 1 0 0 0 1 +SPEAKER +P 400 1200 0 1200 1 0 1 +{ +T 50 1250 5 10 0 1 0 0 1 +pinnumber=1 +T 50 1250 5 10 0 0 0 0 1 +pinseq=1 +T 50 1250 5 10 0 1 0 0 1 +pinlabel=1 +T 50 1250 5 10 0 1 0 0 1 +pintype=pas +} +P 400 800 0 800 1 0 1 +{ +T 0 850 5 10 0 1 0 0 1 +pinnumber=2 +T 0 850 5 10 0 0 0 0 1 +pinseq=2 +T 0 850 5 10 0 1 0 0 1 +pinlabel=2 +T 0 850 5 10 0 1 0 0 1 +pintype=pas +} +B 400 700 300 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2000 2500 5 10 0 0 0 0 1 +device=SPEAKER +L 700 1300 1000 1500 3 0 0 0 -1 -1 +L 700 700 1000 500 3 0 0 0 -1 -1 +T 300 1500 8 10 1 1 0 0 1 +refdes=SPK? diff --git a/custom_symbols/switch-1.fpt b/custom_symbols/switch-1.fpt new file mode 100644 index 0000000..a8a4a48 --- /dev/null +++ b/custom_symbols/switch-1.fpt @@ -0,0 +1,12 @@ + +Element["" "" "" "" 51000 63000 0 0 0 100 ""] +( + Pin[0 -10000 6000 3000 6000 2800 "" "1" ""] + Pin[0 0 6000 3000 6000 2800 "" "C" ""] + Pin[0 10000 6000 3000 6000 2800 "" "2" ""] + ElementLine [4000 20000 4000 -20000 1000] + ElementLine [4000 -20000 22000 -20000 1000] + ElementLine [22000 -20000 22000 20000 1000] + ElementLine [22000 20000 4000 20000 1000] + + ) diff --git a/custom_symbols/switch-spst-1.sym b/custom_symbols/switch-spst-1.sym new file mode 100644 index 0000000..fb4ad99 --- /dev/null +++ b/custom_symbols/switch-spst-1.sym @@ -0,0 +1,28 @@ +v 20110115 2 +L 200 0 600 200 3 0 0 0 -1 -1 +T 400 700 5 10 0 0 0 0 1 +device=SPST +P 600 0 800 0 1 0 1 +{ +T 650 50 5 8 1 1 0 0 1 +pinnumber=2 +T 650 50 5 8 0 0 0 0 1 +pinseq=2 +T 650 50 5 8 0 1 0 0 1 +pinlabel=2 +T 650 50 5 8 0 1 0 0 1 +pintype=pas +} +P 200 0 0 0 1 0 1 +{ +T 100 50 5 8 1 1 0 0 1 +pinnumber=1 +T 100 50 5 8 0 0 0 0 1 +pinseq=1 +T 100 50 5 8 0 1 0 0 1 +pinlabel=1 +T 100 50 5 8 0 1 0 0 1 +pintype=pas +} +T 300 300 8 10 1 1 0 0 1 +refdes=S? diff --git a/gafrc b/gafrc new file mode 100644 index 0000000..8d577ca --- /dev/null +++ b/gafrc @@ -0,0 +1,9 @@ +; -*-Scheme-*- +;;; +;;; Project specific init file for gaf +;;; + +; Add custom symbol library +(component-library "./custom_symbols") + + diff --git a/light-theremin.pcb b/light-theremin.pcb new file mode 100644 index 0000000..9ed6253 --- /dev/null +++ b/light-theremin.pcb @@ -0,0 +1,1333 @@ +# release: pcb 20110918 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20070407] + +PCB["" 600000 500000] + +Grid[5000.0 0 0 1] +Cursor[100000 195000 0.000000] +PolyArea[3100.006200] +Thermal[0.500000] +DRC[1000 1000 1000 1000 1500 1000] +Flags("nameonpcb,uniquename,clearnew,snappin") +Groups("1,c:2,s:3:4:5:6:7:8") +Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 4500 0 5000 800] + SymbolLine[0 1000 0 3500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 1000 0 2000 800] + SymbolLine[1000 1000 1000 2000 800] +) +Symbol['#' 1200] +( + SymbolLine[0 3500 2000 3500 800] + SymbolLine[0 2500 2000 2500 800] + SymbolLine[1500 2000 1500 4000 800] + SymbolLine[500 2000 500 4000 800] +) +Symbol['$' 1200] +( + SymbolLine[1500 1500 2000 2000 800] + SymbolLine[500 1500 1500 1500 800] + SymbolLine[0 2000 500 1500 800] + SymbolLine[0 2000 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 4000 800] + SymbolLine[1500 4500 2000 4000 800] + SymbolLine[500 4500 1500 4500 800] + SymbolLine[0 4000 500 4500 800] + SymbolLine[1000 1000 1000 5000 800] +) +Symbol['%' 1200] +( + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[1000 2500 1500 2000 800] + SymbolLine[500 2500 1000 2500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[0 5000 4000 1000 800] + SymbolLine[3500 5000 4000 4500 800] + SymbolLine[4000 4000 4000 4500 800] + SymbolLine[3500 3500 4000 4000 800] + SymbolLine[3000 3500 3500 3500 800] + SymbolLine[2500 4000 3000 3500 800] + SymbolLine[2500 4000 2500 4500 800] + SymbolLine[2500 4500 3000 5000 800] + SymbolLine[3000 5000 3500 5000 800] +) +Symbol['&' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 3500 1500 2000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[0 2500 2500 5000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[0 3500 0 4500 800] +) +Symbol[''' 1200] +( + SymbolLine[0 2000 1000 1000 800] +) +Symbol['(' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] +) +Symbol[')' 1200] +( + SymbolLine[0 1000 500 1500 800] + SymbolLine[500 1500 500 4500 800] + SymbolLine[0 5000 500 4500 800] +) +Symbol['*' 1200] +( + SymbolLine[0 2000 2000 4000 800] + SymbolLine[0 4000 2000 2000 800] + SymbolLine[0 3000 2000 3000 800] + SymbolLine[1000 2000 1000 4000 800] +) +Symbol['+' 1200] +( + SymbolLine[0 3000 2000 3000 800] + SymbolLine[1000 2000 1000 4000 800] +) +Symbol[',' 1200] +( + SymbolLine[0 6000 1000 5000 800] +) +Symbol['-' 1200] +( + SymbolLine[0 3000 2000 3000 800] +) +Symbol['.' 1200] +( + SymbolLine[0 5000 500 5000 800] +) +Symbol['/' 1200] +( + SymbolLine[0 4500 3000 1500 800] +) +Symbol['0' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4000 2000 2000 800] +) +Symbol['1' 1200] +( + SymbolLine[0 1800 800 1000 800] + SymbolLine[800 1000 800 5000 800] + SymbolLine[0 5000 1500 5000 800] +) +Symbol['2' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[0 5000 2500 2500 800] + SymbolLine[0 5000 2500 5000 800] +) +Symbol['3' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 2800 1500 2800 800] + SymbolLine[2000 1500 2000 2300 800] + SymbolLine[2000 3300 2000 4500 800] + SymbolLine[2000 3300 1500 2800 800] + SymbolLine[2000 2300 1500 2800 800] +) +Symbol['4' 1200] +( + SymbolLine[0 3500 2000 1000 800] + SymbolLine[0 3500 2500 3500 800] + SymbolLine[2000 1000 2000 5000 800] +) +Symbol['5' 1200] +( + SymbolLine[0 1000 2000 1000 800] + SymbolLine[0 1000 0 3000 800] + SymbolLine[0 3000 500 2500 800] + SymbolLine[500 2500 1500 2500 800] + SymbolLine[1500 2500 2000 3000 800] + SymbolLine[2000 3000 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['6' 1200] +( + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[1500 2800 2000 3300 800] + SymbolLine[0 2800 1500 2800 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3300 2000 4500 800] +) +Symbol['7' 1200] +( + SymbolLine[500 5000 2500 1000 800] + SymbolLine[0 1000 2500 1000 800] +) +Symbol['8' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 3700 0 4500 800] + SymbolLine[0 3700 700 3000 800] + SymbolLine[700 3000 1300 3000 800] + SymbolLine[1300 3000 2000 3700 800] + SymbolLine[2000 3700 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 2300 700 3000 800] + SymbolLine[0 1500 0 2300 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 2300 800] + SymbolLine[1300 3000 2000 2300 800] +) +Symbol['9' 1200] +( + SymbolLine[500 5000 2000 3000 800] + SymbolLine[2000 1500 2000 3000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 2000 3000 800] +) +Symbol[':' 1200] +( + SymbolLine[0 2500 500 2500 800] + SymbolLine[0 3500 500 3500 800] +) +Symbol[';' 1200] +( + SymbolLine[0 5000 1000 4000 800] + SymbolLine[1000 2500 1000 3000 800] +) +Symbol['<' 1200] +( + SymbolLine[0 3000 1000 2000 800] + SymbolLine[0 3000 1000 4000 800] +) +Symbol['=' 1200] +( + SymbolLine[0 2500 2000 2500 800] + SymbolLine[0 3500 2000 3500 800] +) +Symbol['>' 1200] +( + SymbolLine[0 2000 1000 3000 800] + SymbolLine[0 4000 1000 3000 800] +) +Symbol['?' 1200] +( + SymbolLine[1000 3000 1000 3500 800] + SymbolLine[1000 4500 1000 5000 800] + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 2000 800] + SymbolLine[1000 3000 2000 2000 800] +) +Symbol['@' 1200] +( + SymbolLine[0 1000 0 4000 800] + SymbolLine[0 4000 1000 5000 800] + SymbolLine[1000 5000 4000 5000 800] + SymbolLine[5000 3500 5000 1000 800] + SymbolLine[5000 1000 4000 0 800] + SymbolLine[4000 0 1000 0 800] + SymbolLine[1000 0 0 1000 800] + SymbolLine[1500 2000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 3000 3500 800] + SymbolLine[3000 3500 3500 3000 800] + SymbolLine[3500 3000 4000 3500 800] + SymbolLine[3500 3000 3500 1500 800] + SymbolLine[3500 2000 3000 1500 800] + SymbolLine[2000 1500 3000 1500 800] + SymbolLine[2000 1500 1500 2000 800] + SymbolLine[4000 3500 5000 3500 800] +) +Symbol['A' 1200] +( + SymbolLine[0 2000 0 5000 800] + SymbolLine[0 2000 700 1000 800] + SymbolLine[700 1000 1800 1000 800] + SymbolLine[1800 1000 2500 2000 800] + SymbolLine[2500 2000 2500 5000 800] + SymbolLine[0 3000 2500 3000 800] +) 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Line[120000 45000 120000 55000 4000 2000 "clearline"] + Line[120000 55000 95000 80000 4000 2000 "clearline"] + Line[95000 80000 85000 80000 4000 2000 "clearline"] + Line[85000 80000 80000 85000 4000 2000 "clearline"] + Line[80000 85000 80000 95000 4000 2000 "clearline"] + Line[80000 95000 90000 105000 4000 2000 "clearline"] + Line[90000 105000 90000 110000 4000 2000 "clearline"] +) +Layer(2 "solder") +( + Line[110000 110000 110000 105000 4000 2000 "clearline"] + Line[110000 105000 115000 100000 4000 2000 "clearline"] + Line[115000 100000 165000 100000 4000 2000 "clearline"] + Line[165000 100000 170000 105000 4000 2000 "clearline"] + Line[170000 105000 170000 150000 4000 2000 "clearline"] + Line[90000 140000 90000 135000 4000 2000 "clearline"] + Line[90000 135000 95000 130000 4000 2000 "clearline"] + Line[120000 130000 120000 140000 4000 2000 "clearline"] + Line[60000 110000 60000 115000 4000 2000 "clearline"] + Line[60000 115000 70000 125000 4000 2000 "clearline"] + Line[70000 125000 80000 125000 4000 2000 "clearline"] + Line[80000 125000 90000 115000 4000 2000 "clearline"] + Line[90000 115000 90000 110000 4000 2000 "clearline"] + Line[70000 90000 70000 110000 4000 2000 "clearline"] + Line[90000 95000 80000 105000 4000 2000 "clearline"] + Line[80000 105000 80000 110000 4000 2000 "clearline"] + Line[100000 140000 100000 145000 4000 2000 "clearline"] + Line[100000 145000 105000 150000 4000 2000 "clearline"] + Line[105000 150000 125000 150000 4000 2000 "clearline"] + Line[125000 150000 135000 140000 4000 2000 "clearline"] + Line[135000 140000 140000 140000 4000 2000 "clearline"] + Line[80000 140000 80000 135000 4000 2000 "clearline"] + Line[80000 135000 95000 120000 4000 2000 "clearline"] + Line[95000 120000 125000 120000 4000 2000 "clearline"] + Line[125000 120000 135000 110000 4000 2000 "clearline"] + Line[95000 130000 170000 130000 4000 2000 "clearline"] + Line[70000 210000 80000 220000 4000 2000 "clearline"] + Line[80000 220000 160000 220000 4000 2000 "clearline"] + Line[160000 220000 170000 210000 4000 2000 "clearline"] + Line[30000 210000 70000 210000 4000 2000 "clearline"] + Line[70000 125000 70000 210000 4000 2000 "clearline"] + Line[30000 210000 30000 240000 4000 2000 "clearline"] + Line[30000 240000 40000 250000 4000 2000 "clearline"] + Line[160000 250000 180000 250000 4000 2000 "clearline"] + Line[30000 150000 30000 170000 4000 2000 "clearline"] + Line[20000 150000 20000 245000 4000 2000 "clearline"] + Line[20000 245000 40000 265000 4000 2000 "clearline"] + Line[180000 240000 180000 200000 4000 2000 "clearline"] + Line[180000 200000 160000 180000 4000 2000 "clearline"] + Line[160000 180000 160000 160000 4000 2000 "clearline"] + Line[160000 160000 170000 150000 4000 2000 "clearline"] + Line[180000 240000 115000 240000 4000 2000 "clearline"] + Line[115000 240000 90000 265000 4000 2000 "clearline"] + Line[90000 265000 40000 265000 4000 2000 "clearline"] + Line[140000 150000 140000 200000 4000 2000 "clearline"] + Line[140000 200000 130000 210000 4000 2000 "clearline"] + Line[180000 150000 180000 160000 4000 2000 "clearline"] + Line[180000 160000 170000 170000 4000 2000 "clearline"] + Line[30000 20000 50000 20000 4000 2000 "clearline"] + Line[150000 20000 170000 20000 4000 2000 "clearline"] + Line[165000 50000 180000 35000 4000 2000 "clearline"] + Line[180000 35000 180000 20000 4000 2000 "clearline"] + Line[165000 50000 95000 50000 4000 2000 "clearline"] + Line[95000 50000 80000 35000 4000 2000 "clearline"] + Line[80000 35000 80000 30000 4000 2000 "clearline"] + Line[90000 95000 90000 80000 4000 2000 "clearline"] + Line[90000 80000 80000 70000 4000 2000 "clearline"] + Line[120000 70000 120000 100000 4000 2000 "clearline"] + Line[100000 60000 130000 60000 4000 2000 "clearline"] + Line[130000 60000 135000 65000 4000 2000 "clearline"] + Line[135000 65000 135000 90000 4000 2000 "clearline"] + Line[100000 40000 100000 30000 4000 2000 "clearline"] + Line[100000 30000 110000 20000 4000 2000 "clearline"] + Line[100000 110000 100000 75000 4000 2000 "clearline"] + Line[100000 75000 70000 45000 4000 2000 "clearline"] + Line[70000 45000 70000 25000 4000 2000 "clearline"] + Line[70000 25000 75000 20000 4000 2000 "clearline"] + Line[75000 20000 90000 20000 4000 2000 "clearline"] + Line[20000 20000 20000 45000 4000 2000 "clearline"] + Line[20000 45000 65000 90000 4000 2000 "clearline"] + Line[65000 90000 70000 90000 4000 2000 "clearline"] +) +Layer(3 "GND") +( +) +Layer(4 "power") +( +) +Layer(5 "signal1") +( +) +Layer(6 "signal2") +( +) +Layer(7 "signal3") +( +) +Layer(8 "signal4") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( + Line[0 280000 200000 280000 4000 2000 "clearline"] + Line[200000 280000 200000 0 4000 2000 "clearline"] +) +NetList() +( + Net("+9V" "(unknown)") + ( + Connect("LED1-1") + Connect("LED2-1") + Connect("R3-2") + Connect("S1-2") + Connect("U1-2") + Connect("U1-11") + Connect("U1-14") + Connect("SW-1") + ) + Net("AmpIn" "(unknown)") + ( + Connect("C2-2") + Connect("U1-10") + ) + Net("AmpOut" "(unknown)") + ( + Connect("C3-1") + Connect("U1-12") + ) + Net("BATT+" "(unknown)") + ( + Connect("B1-1") + Connect("S1-1") + Connect("SW-C") + ) + Net("GND" "(unknown)") + ( + Connect("B1-2") + Connect("LDR2-1") + Connect("R4-1") + Connect("R5-1") + Connect("R6-1") + Connect("SPK1-2") + Connect("U1-4") + Connect("U1-7") + Connect("U1-9") + ) + Net("OscFeedback" "(unknown)") + ( + Connect("C1-1") + Connect("LDR1-1") + Connect("U1-6") + ) + Net("OscOut" "(unknown)") + ( + Connect("C1-2") + Connect("R2-1") + Connect("U1-1") + Connect("U1-5") + ) + Net("PreAmpIn" "(unknown)") + ( + Connect("LDR2-2") + Connect("Q1-2") + Connect("R2-2") + ) + Net("PreAmpOut" "(unknown)") + ( + Connect("C2-1") + Connect("Q1-1") + Connect("R3-1") + ) + Net("SPK+" "(unknown)") + ( + Connect("C3-2") + Connect("SPK1-1") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("R1-2") + Connect("U1-3") + Connect("U1-8") + Connect("U1-13") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("LDR1-2") + Connect("R1-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("Q1-3") + Connect("R4-2") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("LED2-2") + Connect("R6-2") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("LED1-2") + Connect("R5-2") + ) +) diff --git a/light-theremin.pro b/light-theremin.pro index 1dfe8c0..24616bf 100644 --- a/light-theremin.pro +++ b/light-theremin.pro @@ -1,2 +1,2 @@ schematics light-theremin.sch -output-name board +output-name light-theremin diff --git a/light-theremin.sch b/light-theremin.sch index fd76b02..4b88a3b 100644 --- a/light-theremin.sch +++ b/light-theremin.sch @@ -1,100 +1,290 @@ v 20110115 2 -C 40000 40000 1 0 0 title-B.sym -C 47800 46500 1 0 0 lm555-1.sym +C 40000 40000 0 0 0 title-B.sym +C 49900 42900 1 0 0 gnd-1.sym +N 42000 48500 42400 48500 4 { -T 50100 48900 5 10 0 0 0 0 1 -device=LM555 -T 49600 46500 5 10 1 1 0 0 1 -refdes=U? +T 41400 48100 5 10 0 1 0 0 1 +netname=BATT+ } -C 52900 48500 1 90 0 photo-resistor-1.sym +C 51500 45700 1 0 0 speaker-2.sym { -T 52200 49200 5 10 0 0 90 0 1 -device=PHOTORESISTOR -T 52200 48700 5 10 1 1 90 0 1 -refdes=R? -} -C 52900 47400 1 90 0 photo-resistor-1.sym -{ -T 52200 48100 5 10 0 0 90 0 1 -device=PHOTORESISTOR -T 52200 47600 5 10 1 1 90 0 1 -refdes=R? -} -C 50500 42900 1 0 0 speaker-1.sym -{ -T 52500 45400 5 10 0 0 0 0 1 +T 53500 48200 5 10 0 0 0 0 1 device=SPEAKER -T 51100 44900 5 10 1 1 0 0 1 -refdes=SPK? +T 51800 47200 5 10 1 1 0 0 1 +refdes=SPK1 +T 51600 45800 5 10 1 1 0 0 1 +value=8 Ohm +T 51500 45700 5 10 0 1 0 0 1 +footprint=RCY600 } -C 52800 46300 1 90 0 capacitor-1.sym +C 50300 47300 1 0 0 capacitor-4.sym { -T 52100 46500 5 10 0 0 90 0 1 -device=CAPACITOR -T 52300 46500 5 10 1 1 90 0 1 -refdes=C? -T 51900 46500 5 10 0 0 90 0 1 -symversion=0.1 -} -C 51400 46300 1 90 0 capacitor-1.sym -{ -T 50700 46500 5 10 0 0 90 0 1 -device=CAPACITOR -T 50900 46500 5 10 1 1 90 0 1 -refdes=C? -T 50500 46500 5 10 0 0 90 0 1 -symversion=0.1 -} -C 50000 46200 1 270 0 capacitor-4.sym -{ -T 51100 46000 5 10 0 0 270 0 1 +T 50500 48400 5 10 0 0 0 0 1 device=POLARIZED_CAPACITOR -T 50500 46000 5 10 1 1 270 0 1 -refdes=C? -T 50700 46000 5 10 0 0 270 0 1 +T 50500 47800 5 10 1 1 0 0 1 +refdes=C3 +T 50500 48000 5 10 0 0 0 0 1 symversion=0.1 +T 50800 47800 5 10 1 1 0 0 1 +value=100µ +T 50300 47300 5 10 0 0 0 0 1 +footprint=RCY100P } -C 47300 49700 1 0 1 switch-spst-1.sym +C 49000 46400 1 90 0 capacitor-1.sym { -T 46900 50400 5 10 0 0 0 6 1 +T 48300 46600 5 10 0 0 90 0 1 +device=CAPACITOR +T 48400 47000 5 10 1 1 0 0 1 +refdes=C2 +T 48100 46600 5 10 0 0 90 0 1 +symversion=0.1 +T 48400 46600 5 10 1 1 0 0 1 +value=0.1µ +T 49000 46400 5 10 0 1 0 0 1 +footprint=CK05_type_Capacitor +} +C 46500 44800 1 0 0 capacitor-1.sym +{ +T 46700 45500 5 10 0 0 0 0 1 +device=CAPACITOR +T 46600 45300 5 10 1 1 0 0 1 +refdes=C1 +T 46700 45700 5 10 0 0 0 0 1 +symversion=0.1 +T 47000 45300 5 10 1 1 0 0 1 +value=0.1µ +T 46500 44800 5 10 0 1 0 0 1 +footprint=CK05_type_Capacitor +} +C 45600 46400 1 90 0 resistor-2.sym +{ +T 45250 46800 5 10 0 0 90 0 1 +device=RESISTOR +T 45700 46900 5 10 1 1 0 0 1 +refdes=R1 +T 45700 46700 5 10 1 1 0 0 1 +value=2k2 +T 45600 46400 5 10 0 1 0 0 1 +footprint=R025 +} +C 50100 43400 1 90 0 resistor-2.sym +{ +T 49750 43800 5 10 0 0 90 0 1 +device=RESISTOR +T 50200 43900 5 10 1 1 0 0 1 +refdes=R4 +T 50200 43700 5 10 1 1 0 0 1 +value=200 +T 50100 43400 5 10 0 1 0 0 1 +footprint=R025 +} +C 48200 46400 1 90 0 resistor-2.sym +{ +T 47850 46800 5 10 0 0 90 0 1 +device=RESISTOR +T 47700 46900 5 10 1 1 0 0 1 +refdes=R3 +T 47600 46700 5 10 1 1 0 0 1 +value=10k +T 48200 46400 5 10 0 1 0 0 1 +footprint=R025 +} +C 48000 44900 1 0 0 resistor-2.sym +{ +T 48400 45250 5 10 0 0 0 0 1 +device=RESISTOR +T 48200 45200 5 10 1 1 0 0 1 +refdes=R2 +T 48500 45200 5 10 1 1 0 0 1 +value=8k +T 48000 44900 5 10 1 1 0 0 1 +footprint=R025 +} +C 54600 46200 1 90 0 resistor-2.sym +{ +T 54250 46600 5 10 0 0 90 0 1 +device=RESISTOR +T 54700 46700 5 10 1 1 0 0 1 +refdes=R6 +T 54700 46500 5 10 1 1 0 0 1 +value=350 +T 54600 46200 5 10 0 1 0 0 1 +footprint=R025 +} +C 53600 46200 1 90 0 resistor-2.sym +{ +T 53250 46600 5 10 0 0 90 0 1 +device=RESISTOR +T 53700 46700 5 10 1 1 0 0 1 +refdes=R5 +T 53700 46500 5 10 1 1 0 0 1 +value=350 +T 53600 46200 5 10 0 1 0 0 1 +footprint=R025 +} +C 49400 44500 1 0 0 2N3904-2.sym +{ +T 50260 44787 5 10 1 1 0 0 1 +device=2N3904 +T 50300 45000 5 10 1 1 0 0 1 +refdes=Q1 +T 50304 45406 5 10 0 0 0 0 1 +footprint=TO92 +} +C 45900 45300 1 90 0 ldr-1.sym +{ +T 45550 45700 5 10 0 0 90 0 1 +device=RESISTOR +T 44700 45600 5 10 1 1 0 0 1 +refdes=LDR1 +T 44600 45400 5 10 1 1 0 0 1 +device=905014 +T 44500 45200 5 10 1 1 0 0 1 +footprint=ACY100 +} +C 49600 43500 1 90 0 ldr-1.sym +{ +T 49250 43900 5 10 0 0 90 0 1 +device=RESISTOR +T 48400 43800 5 10 1 1 0 0 1 +refdes=LDR2 +T 48300 43600 5 10 1 1 0 0 1 +device=905014 +T 48300 43400 5 10 1 1 0 0 1 +footprint=ACY100 +} +C 43000 46800 1 0 0 4007-2.sym +{ +T 43000 48100 5 10 1 1 0 0 1 +refdes=U1 +T 43800 51600 5 10 0 0 0 0 1 +device=4007 +T 43800 52000 5 10 0 0 0 0 1 +footprint=DIP14 +} +N 45500 46100 45500 46400 4 +N 44000 47300 44000 47700 4 +N 44000 47500 46000 47500 4 +N 45500 47300 45500 47500 4 +N 43000 47500 43000 45000 4 +N 43000 45000 46500 45000 4 +{ +T 43000 45000 5 10 0 1 0 0 1 +netname=OscFeedback +} +N 45500 45000 45500 45300 4 +N 47000 47300 47000 47700 4 +N 47000 47500 47500 47500 4 +N 47500 47500 47500 45000 4 +N 47400 45000 48000 45000 4 +{ +T 47400 45000 5 10 0 1 0 0 1 +netname=OscOut +} +N 43200 48500 54500 48500 4 +{ +T 43200 48500 5 10 0 1 0 0 1 +netname=+9V +} +N 50000 48500 50000 48100 4 +N 47000 48100 47000 48500 4 +N 44000 48100 44000 48500 4 +N 49000 47500 48800 47500 4 +N 50000 45500 50000 45900 4 +N 48100 45900 50000 45900 4 +{ +T 48100 45900 5 10 0 1 0 0 1 +netname=PreAmpOut +} +N 48900 45000 49400 45000 4 +{ +T 48900 45000 5 10 0 1 0 0 1 +netname=PreAmpIn +} +N 49200 44300 49200 45000 4 +C 43900 46400 1 0 0 gnd-1.sym +C 46900 46400 1 0 0 gnd-1.sym +C 49900 46400 1 0 0 gnd-1.sym +N 50000 46700 50000 46900 4 +N 48800 47500 48800 47300 4 +{ +T 48800 47500 5 10 0 1 0 0 1 +netname=AmpIn +} +N 48800 45900 48800 46400 4 +N 48100 46400 48100 45900 4 +N 48100 47300 48100 48500 4 +N 44000 46700 44000 46900 4 +N 47000 46700 47000 46900 4 +N 50000 44300 50000 44500 4 +N 49200 43200 50000 43200 4 +N 50000 43200 50000 43400 4 +N 49200 43200 49200 43500 4 +N 50000 47500 50300 47500 4 +{ +T 50000 47500 5 10 0 1 0 0 1 +netname=AmpOut +} +C 51400 45400 1 0 0 gnd-1.sym +N 51200 47500 51500 47500 4 +N 51500 47500 51500 46900 4 +{ +T 51500 47500 5 10 0 1 0 0 1 +netname=SPK+ +} +N 51500 46500 51500 45700 4 +N 53500 48200 53500 48500 4 +N 54500 48200 54500 48500 4 +N 53500 47300 53500 47100 4 +N 54500 47300 54500 47100 4 +C 53400 45400 1 0 0 gnd-1.sym +N 53500 45700 53500 46200 4 +N 54500 46200 54500 46000 4 +N 54500 46000 53500 46000 4 +C 54400 48200 1 270 0 led-2.sym +{ +T 54700 47800 5 10 1 1 0 0 1 +refdes=LED2 +T 55000 48100 5 10 0 0 270 0 1 +device=LED +T 54400 48200 5 10 0 1 0 0 1 +footprint=T1.75_LED +} +C 53400 48200 1 270 0 led-2.sym +{ +T 53700 47800 5 10 1 1 0 0 1 +refdes=LED1 +T 54000 48100 5 10 0 0 270 0 1 +device=LED +T 53400 48200 5 10 0 1 0 0 1 +footprint=T1.75_LED +} +C 42400 48500 1 0 0 switch-spst-1.sym +{ +T 42800 49200 5 10 0 0 0 0 1 device=SPST -T 47000 50000 5 10 1 1 0 6 1 -refdes=S? +T 42700 48800 5 10 1 1 0 0 1 +refdes=S1 +T 42400 48500 5 10 0 0 0 0 1 +footprint=switch-1 } -C 52500 45800 1 0 0 gnd-1.sym -C 45500 49500 1 90 0 generic-power.sym +C 41800 47500 1 270 0 battery-3.sym { -T 45250 49700 5 10 1 1 90 3 1 -net=Vcc:1 +T 42500 47200 5 10 0 0 270 0 1 +device=BATTERY +T 41400 47000 5 10 1 1 0 0 1 +refdes=B1 +T 42750 47200 5 10 0 0 270 0 1 +symversion=0.1 +T 41400 46800 5 10 1 1 0 0 1 +value=9V +T 41100 46600 5 10 1 1 0 0 1 +footprint=ACY1200 } -N 52600 48300 52600 48500 4 -N 52600 47200 52600 47400 4 -N 52600 46100 52600 46300 4 -N 50100 47600 51200 47600 4 -N 51200 47600 51200 47200 4 -C 51100 45800 1 0 0 gnd-1.sym -N 51200 46100 51200 46300 4 -N 50100 48400 52600 48400 4 -N 52600 49400 52600 49700 4 -N 47300 49700 52600 49700 4 -N 49400 49700 49400 49300 4 -N 45500 49700 46500 49700 4 -N 50100 48000 51800 48000 4 -N 51800 48000 51800 47300 4 -N 51800 47300 52600 47300 4 -N 48600 49300 48600 49700 4 -N 50100 46900 50200 46900 4 -N 50200 44800 50500 44800 4 -N 50200 46900 50200 46200 4 -N 50200 45300 50200 44800 4 -N 50500 43600 50200 43600 4 -N 50200 43600 50200 43300 4 -C 50100 43000 1 0 0 gnd-1.sym -N 47800 48000 47500 48000 4 -N 47500 48000 47500 49500 4 -N 47500 49500 50700 49500 4 -N 50700 49500 50700 48400 4 -C 47400 46200 1 0 0 gnd-1.sym -N 47500 46500 47500 46900 4 -N 47500 46900 47800 46900 4 +C 41900 45200 1 0 0 gnd-1.sym +N 42000 48500 42000 47500 4 +{ +T 41800 48600 5 10 0 1 0 0 1 +netname=BATT+ +} +N 42000 46400 42000 45500 4